Design → Tapeout
IP licensing, architecture definition, logic synthesis, place & route, verification, and handoff to foundry
Processor Core IP
PHY & Interface IP HBM4 PHY
Chip Owner / Architecture
Hyperscaler Custom Chips
EDA Toolchain
Signoff / Verification
Leading-Edge Foundry + PDK N3P
Photomasks / Reticles
Translating tapeout data into physical masks, including pellicle protection and actinic inspection
EUV Mask Blanks
Mask Writers (Multi-beam E-beam)
EUV Pellicles
Mask Shops (Merchant)
EUV Mask Inspection
Wafer Fabrication
FEOL transistor formation and BEOL interconnect metallization — hundreds of process steps at 3 nm / 2 nm nodes
Leading-Edge Logic Fab N3P
300 mm Silicon Wafers
Photoresists / Litho Chemicals
Ultra-High-Purity Gases
Filters / Fluid Handling
Slurry & Polishing Pads
Sputter Targets & Precursors
EUV Lithography Stack
CVD / PVD / ALD
Plasma Etch
Ion Implantation
Chemical-Mechanical Planarization
Wet Cleaning / Surface Prep
Coat-Develop Track
Inspection / Metrology
Wafer Sort (Probe Test)
Electrically testing every die on the wafer to identify known-good die. Advantest + Teradyne hold >50% of ATE market.
Testers (ATE)
Probe Cards
Handlers / Automation
Die Preparation
Thinning wafers to <50 μm for 2.5D/3D stacking, then dicing into individual known-good die. DISCO dominates both segments.
Wafer Backgrinding
Wafer Dicing / Singulation
Advanced Packaging CoWoS-L
CoWoS-class 2.5D integration — bonding GPU die + HBM4 stacks onto a silicon interposer. Rubin uses CoWoS-L at 3.5x reticle size.
HBM Stacks HBM4
2.5D Interposer Platform CoWoS-L
Advanced Packaging Lithography
Hybrid & TC Bonders HBM4
Underfill, Solder & TIMs
Molding Compounds & Encapsulants
ABF Substrates (HPC Grade)
Advanced Packaging at Scale
Final Package Test / Burn-in
IC Test Sockets & Contactors
GPU Module Assembly
Mounting the packaged GPU onto a module board with power delivery and thermal solution (SXM / OAM form factor)
Module Board / PCB
Power Delivery (VRMs) 800V DC
Thermal / Liquid Cooling
System Integration & Networking
Assembling GPU modules into AI servers and connecting them with Tbps networking. Taiwan ODMs build >90% of AI servers. Networking = 20-30% of cluster cost.
Server / System Integration
Intra-Node Interconnect NVLink 6
Inter-Node Network Fabric
Optical Transceivers (800G/1.6T)
Data Center Infrastructure
Everything required to house, power, cool, and connect AI compute at scale
Power Infrastructure
Grid connection through power distribution — the #1 constraint on AI data center buildout. Transformer lead times: 2–4 years.
Utility Providers
Power Transformers (HV/MV)
Switchgear & Circuit Breakers
UPS Systems
Backup Generators
Power Distribution Units (PDUs)
Busbars & Busway Systems
Battery Energy Storage (BESS)
On-Site Generation (Fuel Cells & SMRs)
Cooling Infrastructure
From precision air cooling to mandatory liquid cooling for 1,800W AI GPUs. Liquid cooling now captures 46% of DC cooling market.
Precision Cooling (CRAC / CRAH)
Liquid Cooling (Direct-to-Chip & Immersion)
Industrial Chillers
Cooling Towers & Dry Coolers
Data Center Networking
Switches, NICs, silicon, and cabling connecting every GPU. Broadcom holds ~75% monopoly in switch ASICs — the hidden bottleneck.
Data Center Ethernet Switches
Ethernet Switch ASICs
Network Interface Cards & DPUs
Fiber Optic Cabling
Structured Cabling
Facility Infrastructure
Racks, fire suppression, security, monitoring, construction, and modular deployment — the physical shell of the data center
Server Racks & Cabinets
Fire Suppression Systems
Physical Security & Access Control
Infrastructure Management Software
DC Design & Construction (EPC)
Modular / Prefab Data Centers
Colocation & Hyperscale Operators
The end-customers housing and operating AI compute. Combined hyperscaler capex: $315B+ in 2025. Power — not capital — is the binding constraint.